1. Field of the Invention
The present invention relates to latch circuits, and more particularly to a dynamic logic return-to-zero (RTZ) latching mechanism for logic evaluation functions, where the latching mechanism exhibits a significantly reduced data-to-output time.
2. Description of the Related Art
The complexity of pipelined architectures has grown along with the complexity of logical evaluations required within the individual stages of such architectures. And, since speed is a critical factor in pipelined architectures, more and more work is required to be performed within each stage in less and less time. Numerous techniques have been developed to allow this work to be done within the allotted time. In exemplary techniques, the work is divided between stages and inputs are provided with reduced setup time requirements in subsequent stages so that logic in a preceding stage is provided with the time to complete its logical evaluation. Such techniques, however, only compensate in multiple/subsequent stages for the amount of time that is required to perform a given logical evaluation. In other words, they only treat the symptoms resulting from present day logic techniques that are employed within pipelined systems to perform complex evaluations. The real problem is that present day logic evaluation circuits (e.g., multiplexers, encoders, decoders, bit comparators, etc.) take too long to generate their outputs.
Logical evaluation circuits have associated setup time and hold time requirements for their input data, and they additionally have corresponding clock-to-output time characteristics. The “speed” of a given logic circuit is typically judged in terms of its data-to-output time, that is, the sum of its setup time and clock-to-output time. In a pipelined system, the cumulative effect of slow logic evaluation functions in each stage of the pipeline is a system that exhibits a significantly slower operating speed than would otherwise be desirable.